Memory devices are used in a variety of electronic systems including computers, cellular phones, pagers, personal digital assistants, avionic systems, automotive systems, industrial control systems, appliances, etc. Depending on the particular system configuration, the memory devices may be either non-volatile or volatile. A non-volatile memory device retains the data or instructions when the device is turned off or power is removed. A volatile memory device, on the other hand, does not retain the stored data or instructions when the device is turned off. Flash memory has become an important type of non-volatile memory because it is less expensive to manufacture and has a higher device density than most other types of memory devices. In addition, Flash memory is electrically erasable and has a life span of up to one million write cycles.
As semiconductor device manufacturers shrink memory devices such as Flash memories and Dynamic Random Access Memories (DRAM's), the charge storage area in these devices decreases resulting in fewer stored electrons. One technique for increasing the number of stored electrons has been to incorporate nanocrystals in the charge storage region of a memory device. FIG. 1 illustrates a prior art memory device 10 having a layer of nanocrystal material disposed in the charge storage region. What is shown in FIG. 1 is a semiconductor substrate 12 on which a gate structure 14 is formed. Gate structure 14 includes a gate conductor 22 disposed on a dielectric stack comprising a tunnel oxide layer 16, a metal nanocrystal layer 18, and a control oxide layer 20. Source and drain regions 24 and 26, respectively, are formed in the portions of substrate 12 adjacent gate structure 14. Metal nanocrystal layer 18 is formed by depositing a thin metal layer on tunnel oxide layer 16 and annealing the metal at high temperatures to cause the metal to agglomerate. Each metal agglomerate is a nanocrystal. The thin metal layer from which the nanocrystals are formed is typically gold, platinum silicide, silver, or nickel.
A drawback with this procedure is that the agglomeration process is random, thus there is a large variation in the size and spacial distribution of the nanocrystals. In addition, the mean size of the nanocrystal is sensitive to the local temperature and metal film thickness, making it difficult to control their size distribution on large diameter semiconductor wafers. Because the threshold voltage (Vt) is dependent on the size of the nanocrystals, a large variation in nanocrystal size results in a large variation in the threshold voltage across the semiconductor wafer. Another drawback is that formation of the control oxide layer oxidizes the nanocrystals, which degrades their charge storage capacities. Other drawbacks of using the agglomeration process include the cost and complexity of using metals such as gold, platinum silicide, silver, and nickel to form the thin metal layer and the inability of the control oxide to sufficiently fill the spaces between small dimension nanocrystals.
Accordingly, it would be advantageous to have a method for manufacturing a charge storage structure having nanocrystals with a uniform size and that limits the oxidation of the nanocrystals. It would be of further advantage for the structure and method to be cost and time efficient and compatible with memory device manufacturing processes.